Design of S-Band Frequency Synthesizer for Microwave Applications

A phase locked loop based indirect frequency synthesizer is designed for S-band frequency. A Phase locked loop is designed and the phase noise response and transient response of the designed PLL is simulated for 2100MHz frequency. The phase noise response of total PLL and its individual components are obtained. A 3rd order low pass passive loop filter is used and by varying the loop bandwidth and phase margin the trade-off between lock time and phase noise is observed and an optimum value of loop bandwidth and phase margin is chosen such that its phase noise contribution is less. The designed phase locked loop has a low phase noise value of -112.4dBc/Hz at 100 kHz offset frequency and has a fast lock time of 119.5 us. The time taken by the designed frequency synthesizer to lock to 10 Hz frequency error and 1° phase error under transient conditions is found to be 149 us and 116 us respectively. The RMS phase jitter obtained for the designed phase locked loop is 0.3° rms. The phase locked loop is designed and simulated using ADIsimPLL tool. The phase locked loop design aims at achieving low phase noise, reduced lock time and high reliability for S-band applications.