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COMPLEMENTARY PASS TRANSISTOR LOGIC SYNTHESIS WITH 123 DECISION DIAGRAM

Journal Name:

  • Istanbul University Journal of Electrical & Electronics Engineering

Publication Year:

  • 2004

Key Words:

Author NameUniversity of Author
Abstract (2. Language): 
123 decision diagram is a very effective PTL synthesis tool based on binary decision diagram. It realizes a logic function using NMOS pass transistors with CMOS restoring buffers. In this paper the 123 decision diagram is applied to realize CMOS pass transistor logic circuits without restoring buffers. Cell circuits for the 4 bit adder is realized with the CMOS pass transistors using the 123 decision diagram and 4 bit adder is completed by combining the cells.
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  • 1
1045- 1049
  • English

REFERENCES

References: 

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[7] Yano K., Sasaki Y., Rikino K., Seki K., “Top Down Pass Transistor Logic Design”, IEEE Jour. of Solid State Circuits, Vol 31, Iss 6, pp 792-803, 1996.

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