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A FAST MULTIPLIER HARDWARE DESIGN FOR INTERVAL ARITHMETIC

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Abstract (2. Language): 
In this paper, a new parallel hardware unit for interval multiplication is presented. Using the VHDL synthesis results, the area and delay estimates for the new design are given. Compared to previous hardware interval multipliers, our design is faster, but, requires more area.
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REFERENCES

References: 

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Ahmet SERTBAŞ,

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