Journal Name:
- Cumhuriyet Üniversitesi Fen Fakültesi Fen Bilimleri Dergisi
Key Words:
| Author Name | University of Author | Faculty of Author |
|---|---|---|
Abstract (2. Language):
A dynamic, single-edge-triggered D-type flip-flop (SETDFF) is evaluated for implementation of a successive
approximation register analog-to-digital converter intended for biomedical implant devices. The performance of the
dynamic SETDFF in a 90nm CMOS technology has been compared to that of a static D-type SETDFF topology
employing master-slave latches based on SPICE simulations. Both flip-flop types have been designed and implemented
in a 2μm CMOS technology and their performance has been characterized. Compared with the static flip-flop
implemented with master-slave latches, the dynamic flip-flop consumes less power, employs a smaller number of
transistors and is capable of operating at slightly higher speeds. A dual-edge-triggered flip-flop topology based on the
given dynamic flip-flop architecture is proposed in order to further reduce power consumption.
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FULL TEXT (PDF):
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