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A PERFORMANCE ANALYSIS OF CLASSIFIED BINARY ADDER ARCHITECTURES AND THE VHDL SIMULATIONS

Journal Name:

  • Istanbul University Journal of Electrical & Electronics Engineering

Publication Year:

  • 2004

Key Words:

Author NameUniversity of Author
Abstract (2. Language): 
In this paper, the four binary adder architectures belong to a different adder class are studied and compared with each other to analyse their performances. Comparisons include the unit-gate models for area and delay. As the performance measure, the product of the area and the delay is used. By a VHDL simulator, the adder structures are simulated to verify the functional correctness and to measure delay times.
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  • 1
1025-1030
  • English

REFERENCES

References: 

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[2] R.W. Doran: ‘Variants of an Improved Carry Look-Ahead Adder’, IEEE Trans. On Computers, 37, pp. 1110-1113, 1988.
[3] J.Sklansky.: ‘Conditional Sum Addition Logic’, IRE Trans. EC-9 No. 2 , 1960.
[4] R.P. Brent, and H.T. Kung: ‘A Regular Layout for Parellel Adders’, IEEE Trans. Comput. C-31, 1982.
[5] T.Lynch and E.jr.Swartzlander : ‘A Spanning Tree Carry Lookahead Adder’, IEEE Trans. Comput., vol. 41. No. 8 , 1992.
[6] H. Ling: ‘High-Speed Binary Adder’, IBM J. Res.Develop., vol. 25. , 1981.
[7] R. Zimmerman: ‘Binary Adder Architectures for Cell-Based VLSI and their Synthesis Acknowledgments’, Phd. Thesis, Swiss Federal Inst. Of Tech., Zurich, 1997.
[8] B.Parhami:‘Computer Arithmetic Algorithms and Hardware Designs, Oxford University Press, 2000.
[9] Altera Corperation, MAX Plus II Data Sheets, http://www.altera.com.

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